1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for fabricating the same, and in particular, to a metal oxide semiconductor (MOS) transistor and the fabricating method thereof.
2. Description of Related Art
Along with rapid progress of semiconductor technology, the dimensions of semiconductor devices are reduced and the integrity thereof is promoted continuously to further advance the operating speed and performance of the integrated circuit. As the demand for device integrity is raised, dramatic changes in the device characteristics, e.g. current leakage, hot carrier effect and short channel effect (SCE), have to be considered so as to avoid a great impact on reliability and performance of the circuit.
Taking a MOS transistor as an example, FIG. 1 is a schematic cross-sectional view illustrating a conventional MOS transistor. As shown in FIG. 1, a gate structure 102 is disposed on a substrate 100. A pair of spacers 104 is disposed on the sidewalls of the gate structure 102. A pair of the source drain extension (SDE) offset spacers 106 are formed between the gate structure 102 and the spacers 104, and also between the spacers 104 and the substrate 100. A source region 108a and a drain region 108b, jointly as source drain (SD), are disposed in the substrate 100 at respective outer sides of the spacers 104. A source extension region 110a and a drain extension region 110b, jointly as the SDE, are disposed in the substrate 100 under the spacers 104. In other words, the source extension region 110a is deployed between the source region 108a and the gate structure 102, while the drain extension region 110b is deployed between the drain region 108b and the gate structure 102. A salicide layer 112 is disposed on the gate structure 102, the source region 108a and the drain region 108b. 
Considering the concentration of the source and drain extension regions 110a and 110b, which play important roles on the device performance, the dosage for the source and drain extension regions 110a and 110b must be heavy enough to ensure the performance of the device. The heavily-doped source and drain extension regions 110a and 110b, however, results in higher gate-induced drain leakage (GIDL) current and severe hot carrier effect. Although GIDL and hot carrier effect can be reduced by decreasing the dosage of the SDE, the sheet resistance and gate-drain overlap capacitance thereof are raised; which affect device performance significantly. Furthermore, spacers 104 must be thick enough to prevent the dopant in the source and drain regions 108a and 108b from diffusing to the SDE, and sufficient space has to be reserved for the SD diffusion so that punch through and short channel effect (SCE) can be well suppressed. Besides, when a stress liner film may be formed on the substrate 100, the stress liner film lies apart from the channel region due to the thicker spacers 104. Accordingly, the mobility enhancement attributed to the stress liner film is degraded.
As a result, how to effectively ensure the reliability and also enhance the device performance is one of the immediate issues to be solved in the art.